;**********************************************************************
;   This file is a basic code template for assembly code generation   *
;   on the PIC16F887. This file contains the basic code               *
;   building blocks to build upon.                                    *
;                                                                     *
;   If interrupts are not used all code presented between the ORG     *
;   0x004 directive and the label main can be removed. In addition    *
;   the variable assignments for 'w_temp' and 'status_temp' can       *
;   be removed.                                                       *
;                                                                     *
;   Refer to the MPASM User's Guide for additional information on     *
;   features of the assembler (Document DS33014).                     *
;                                                                     *
;   Refer to the respective PIC data sheet for additional             *
;   information on the instruction set.                               *
;                                                                     *
;**********************************************************************
;                                                                     *
;    Filename:	    Final Project.asm                                 *
;    Date:          5/27/2012                                         *
;    File Version:  4                                                 *
;                                                                     *
;    Author:        	                                  *
;    Company:       University of Cincinnati                          *
;                                                                     *
;                                                                     *
;**********************************************************************
;                                                                     *
;    Files required:                                                  *
;                                                                     *
;                                                                     *
;                                                                     *
;**********************************************************************
;                                                                     *
;    Notes:                                                           *
;                                                                     *
;                                                                     *
;                                                                     *
;                                                                     *
;**********************************************************************



	list		p=16f887	; list directive to define processor
	#include	<p16f887.inc>	; processor specific variable definitions


; '__CONFIG' directive is used to embed configuration data within .asm file.
; The labels following the directive are located in the respective .inc file.
; See respective data sheet for additional information on configuration word.

	__CONFIG    _CONFIG1, _LVP_OFF & _FCMEN_OFF & _IESO_OFF & _BOR_OFF & _CPD_OFF & _CP_OFF & _MCLRE_OFF & _PWRTE_ON & _WDT_OFF & _INTRC_OSC_NOCLKOUT
	__CONFIG    _CONFIG2, _WRT_OFF & _BOR21V


	cblock     0x20
Delay1								; used in debounce
Delay2								; used in debounce

Max
DisplayX
DisplayY
DisplayXMax
DisplayYMax
DisplayMag
MaxX								; Stores X max voltage
MaxY								; Stores Y max voltage
Subtract
;A/D conversion
Voltage								; records moving voltage

temp								; look up table variable
	endc

; Flag Definitions
	cblock 0x70     				; put these up in unbanked RAM
W_Save								
STATUS_Save	

;MaxX								; Stores X max voltage
;MaxY								; Stores Y max voltage						
	endc							

org 0								; Program Start
	goto		main

org 4
ISR   
	movwf		W_Save				; Save context
	movf		STATUS,w
	movwf		STATUS_Save           
Button
	bcf			STATUS,RP0			; Ensure ISR executes in Register Bank 0
	bcf			STATUS,RP1
	call		Delay				; debounce
    bcf         INTCON, INTF		; clear the interrupt flag. (must be done in software)

; put other functions here

	goto		ExitISR
               
ExitISR
	movf		STATUS_Save,w		; Restore context
	movwf		STATUS
	swapf		W_Save,f			; swapf doesn't affect Status bits, but MOVF would
	swapf		W_Save,w
	retfie

Delay								; for debounce and display delay
	movwf		Delay2
DelayLoop
	decfsz		Delay1,f			; Waste time.  
	goto		DelayLoop			; The Inner loop takes 3 instructions per loop * 256 loopss = 768 instructions
	decfsz		Delay2,f			; The outer loop takes and additional 3 instructions per lap * 256 loops
	goto		DelayLoop			; (768+3) * 256 = 197376 instructions / 1M instructions per second = 0.197 sec.
									; call it two-tenths of a second.
	return
    
Init
	bsf			STATUS,RP0			; Select Register Bank 1
	movlw     	0xFF
    movwf     	TRISA               ; Make PortA all input
	clrf		TRISC				; Make ProtC an output
	clrf		TRISD				; Make ProtD an output
    movlw       0xFF
    movwf       TRISB               ; Make RB0 pin input for button

	movlw		0x00				; Left Justified, Vdd-Vss referenced
	movwf		ADCON1
	bsf			STATUS,RP1			; select Register Bank 3
	movlw		0xFF				; we want all Port A pins Analog
	movwf		ANSEL
    movlw       0x00
    movwf       ANSELH              ; PortB pins are digitial (important as RB0 is switch)

	bcf			STATUS,RP0			; back to Register Bank 0
	bcf			STATUS,RP1
    movlw       B'10010000'         ; enable global interrupts, and button inturrupt
    movwf       INTCON
	movlw		0x41
	movwf		ADCON0				; configure A2D for Fosc/8, Channel 0 (RA0), and turn on the A2D module

	clrf		MaxX
	clrf		Subtract
	clrf		MaxY
	clrf		Voltage
	clrf		DisplayX
	clrf		DisplayY
	clrf		DisplayXMax
	clrf		DisplayYMax
	clrf		DisplayMag
	clrf		Max

	bsf			DisplayX,0			; testing flag to enter program
	return							; Returns to main

XVoltage							; Module for X Voltage
	nop								; wait 5uS for A2D amp to settle and capacitor to charge.
	nop								; wait 1uS
	nop								; wait 1uS
	nop								; wait 1uS 
	nop								; wait 1uS
	bsf			ADCON0,GO_DONE		; start conversion
	btfss		ADCON0,GO_DONE		; this bit will change to zero when the conversion is complete
	goto		$-1

	movf		ADRESH,w			; Copy the display to the LEDs
	movwf		Voltage

	call		BCDRightDigit
;	movf		MaxX,0				; tests xmax value, to do so comment out BCDRight call.
	movwf		PORTD				; moves working to display for port D
	movf		Voltage,0			; moves voltage back to file register

	call		BCDLeftDigit		; call left number look up table
	movwf		PORTC				; moves the look up table value to port c
	movf		Voltage,0			; moves voltage back to file register

	subwf		MaxX,0				; subtracts voltage and Xmax to with 2s compliment
	btfsc		STATUS,C			; stores largest value
	Call		MainLoop			; calls main loop
	
	movf		Voltage,0			; moves voltage back to file register
	movwf		MaxX				

	goto		MainLoop			; Returns to MainLoop


main
	Call		Init				; Calls the Input and output decleration

MainLoop							; main loop
	btfsc		DisplayX,0			; tests value to move into X mod or move on
	goto		XVoltage			; Calls X Voltage Module
	goto		MainLoop			; go to main loop

	org			0xf7				; force table to cross a 256 instruction boundary
BCDLeftDigit						; look up table call for left digit
	movwf		temp
	movlw		high LeftDigitLookUpTable	; get high order part of the beginning of the table
	movwf		PCLATH
	movlw		low LeftDigitLookUpTable	; load starting address of table
	addwf		temp,w				; add offset
	btfsc		STATUS,C			; did it overflow?
	incf		PCLATH,f			; yes: increment PCLATH
	movwf		PCL					; modify PCL
	Return

BCDRightDigit						; look up table call for right digit
	movwf		temp
	movlw		high RightDigitLookUpTable	; get high order part of the beginning of the table
	movwf		PCLATH
	movlw		low RightDigitLookUpTable	; load starting address of table
	addwf		temp,w				; add offset
	btfsc		STATUS,C			; did it overflow?
	incf		PCLATH,f			; yes: increment PCLATH
	movwf		PCL					; modify PCL

RightDigitLookUpTable				; BCD conversion table
	retlw		b'01111110' ; 0		0
	retlw		b'01111110' ; 0
	retlw		b'01111110' ; 0
	retlw		b'01111110' ; 0
	retlw		b'01111110' ; 0
	retlw		b'00001100' ; 1
	retlw		b'00001100' ; 1
	retlw		b'00001100' ; 1
	retlw		b'00001100' ; 1
	retlw		b'00001100' ; 1
	retlw		b'10110110' ; 2
	retlw		b'10110110' ; 2
	retlw		b'10110110' ; 2
	retlw		b'10110110' ; 2
	retlw		b'10110110' ; 2
	retlw		b'10011110' ; 3
	retlw		b'10011110' ; 3
	retlw		b'10011110' ; 3
	retlw		b'10011110' ; 3
	retlw		b'10011110' ; 3
	retlw		b'11001100' ; 4
	retlw		b'11001100' ; 4
	retlw		b'11001100' ; 4
	retlw		b'11001100' ; 4
	retlw		b'11001100' ; 4
	retlw		b'11011010' ; 5
	retlw		b'11011010' ; 5
	retlw		b'11011010' ; 5
	retlw		b'11011010' ; 5
	retlw		b'11011010' ; 5
	retlw		b'11111010' ; 6
	retlw		b'11111010' ; 6
	retlw		b'11111010' ; 6
	retlw		b'11111010' ; 6
	retlw		b'11111010' ; 6
	retlw		b'00001110' ; 7
	retlw		b'00001110' ; 7
	retlw		b'00001110' ; 7
	retlw		b'00001110' ; 7
	retlw		b'00001110' ; 7
	retlw		b'11111110' ; 8
	retlw		b'11111110' ; 8
	retlw		b'11111110' ; 8
	retlw		b'11111110' ; 8
	retlw		b'11111110' ; 8
	retlw		b'11001110' ; 9
	retlw		b'11001110' ; 9
	retlw		b'11001110' ; 9
	retlw		b'11001110' ; 9
	retlw		b'11001110' ; 9
	retlw		b'01111110' ; 0		1
	retlw		b'01111110' ; 0
	retlw		b'01111110' ; 0
	retlw		b'01111110' ; 0
	retlw		b'01111110' ; 0
	retlw		b'00001100' ; 1
	retlw		b'00001100' ; 1
	retlw		b'00001100' ; 1
	retlw		b'00001100' ; 1
	retlw		b'00001100' ; 1
	retlw		b'10110110' ; 2
	retlw		b'10110110' ; 2
	retlw		b'10110110' ; 2
	retlw		b'10110110' ; 2
	retlw		b'10110110' ; 2
	retlw		b'10011110' ; 3
	retlw		b'10011110' ; 3
	retlw		b'10011110' ; 3
	retlw		b'10011110' ; 3
	retlw		b'10011110' ; 3
	retlw		b'11001100' ; 4
	retlw		b'11001100' ; 4
	retlw		b'11001100' ; 4
	retlw		b'11001100' ; 4
	retlw		b'11001100' ; 4
	retlw		b'11011010' ; 5
	retlw		b'11011010' ; 5
	retlw		b'11011010' ; 5
	retlw		b'11011010' ; 5
	retlw		b'11011010' ; 5
	retlw		b'11111010' ; 6
	retlw		b'11111010' ; 6
	retlw		b'11111010' ; 6
	retlw		b'11111010' ; 6
	retlw		b'11111010' ; 6
	retlw		b'00001110' ; 7
	retlw		b'00001110' ; 7
	retlw		b'00001110' ; 7
	retlw		b'00001110' ; 7
	retlw		b'00001110' ; 7
	retlw		b'11111110' ; 8
	retlw		b'11111110' ; 8
	retlw		b'11111110' ; 8
	retlw		b'11111110' ; 8
	retlw		b'11111110' ; 8
	retlw		b'11001110' ; 9
	retlw		b'11001110' ; 9
	retlw		b'11001110' ; 9
	retlw		b'11001110' ; 9
	retlw		b'11001110' ; 9
	retlw		b'01111110' ; 0		2
	retlw		b'01111110' ; 0
	retlw		b'01111110' ; 0
	retlw		b'01111110' ; 0
	retlw		b'01111110' ; 0
	retlw		b'00001100' ; 1
	retlw		b'00001100' ; 1
	retlw		b'00001100' ; 1
	retlw		b'00001100' ; 1
	retlw		b'00001100' ; 1
	retlw		b'10110110' ; 2
	retlw		b'10110110' ; 2
	retlw		b'10110110' ; 2
	retlw		b'10110110' ; 2
	retlw		b'10110110' ; 2
	retlw		b'10011110' ; 3
	retlw		b'10011110' ; 3
	retlw		b'10011110' ; 3
	retlw		b'10011110' ; 3
	retlw		b'10011110' ; 3
	retlw		b'11001100' ; 4
	retlw		b'11001100' ; 4
	retlw		b'11001100' ; 4
	retlw		b'11001100' ; 4
	retlw		b'11001100' ; 4
	retlw		b'11011010' ; 5
	retlw		b'11011010' ; 5
	retlw		b'11011010' ; 5
	retlw		b'11011010' ; 5
	retlw		b'11011010' ; 5
	retlw		b'11111010' ; 6
	retlw		b'11111010' ; 6
	retlw		b'11111010' ; 6
	retlw		b'11111010' ; 6
	retlw		b'11111010' ; 6
	retlw		b'00001110' ; 7
	retlw		b'00001110' ; 7
	retlw		b'00001110' ; 7
	retlw		b'00001110' ; 7
	retlw		b'00001110' ; 7
	retlw		b'11111110' ; 8
	retlw		b'11111110' ; 8
	retlw		b'11111110' ; 8
	retlw		b'11111110' ; 8
	retlw		b'11111110' ; 8
	retlw		b'11001110' ; 9
	retlw		b'11001110' ; 9
	retlw		b'11001110' ; 9
	retlw		b'11001110' ; 9
	retlw		b'11001110' ; 9
	retlw		b'01111110' ; 0		3
	retlw		b'01111110' ; 0
	retlw		b'01111110' ; 0
	retlw		b'01111110' ; 0
	retlw		b'01111110' ; 0
	retlw		b'00001100' ; 1
	retlw		b'00001100' ; 1
	retlw		b'00001100' ; 1
	retlw		b'00001100' ; 1
	retlw		b'00001100' ; 1
	retlw		b'10110110' ; 2
	retlw		b'10110110' ; 2
	retlw		b'10110110' ; 2
	retlw		b'10110110' ; 2
	retlw		b'10110110' ; 2
	retlw		b'10011110' ; 3
	retlw		b'10011110' ; 3
	retlw		b'10011110' ; 3
	retlw		b'10011110' ; 3
	retlw		b'10011110' ; 3
	retlw		b'11001100' ; 4
	retlw		b'11001100' ; 4
	retlw		b'11001100' ; 4
	retlw		b'11001100' ; 4
	retlw		b'11001100' ; 4
	retlw		b'11011010' ; 5
	retlw		b'11011010' ; 5
	retlw		b'11011010' ; 5
	retlw		b'11011010' ; 5
	retlw		b'11011010' ; 5
	retlw		b'11111010' ; 6
	retlw		b'11111010' ; 6
	retlw		b'11111010' ; 6
	retlw		b'11111010' ; 6
	retlw		b'11111010' ; 6
	retlw		b'00001110' ; 7
	retlw		b'00001110' ; 7
	retlw		b'00001110' ; 7
	retlw		b'00001110' ; 7
	retlw		b'00001110' ; 7
	retlw		b'11111110' ; 8
	retlw		b'11111110' ; 8
	retlw		b'11111110' ; 8
	retlw		b'11111110' ; 8
	retlw		b'11111110' ; 8
	retlw		b'11001110' ; 9
	retlw		b'11001110' ; 9
	retlw		b'11001110' ; 9
	retlw		b'11001110' ; 9
	retlw		b'11001110' ; 9
	retlw		b'01111110' ; 0		4
	retlw		b'01111110' ; 0
	retlw		b'01111110' ; 0
	retlw		b'01111110' ; 0
	retlw		b'01111110' ; 0
	retlw		b'00001100' ; 1
	retlw		b'00001100' ; 1
	retlw		b'00001100' ; 1
	retlw		b'00001100' ; 1
	retlw		b'00001100' ; 1
	retlw		b'10110110' ; 2
	retlw		b'10110110' ; 2
	retlw		b'10110110' ; 2
	retlw		b'10110110' ; 2
	retlw		b'10110110' ; 2
	retlw		b'10011110' ; 3
	retlw		b'10011110' ; 3
	retlw		b'10011110' ; 3
	retlw		b'10011110' ; 3
	retlw		b'10011110' ; 3
	retlw		b'11001100' ; 4
	retlw		b'11001100' ; 4
	retlw		b'11001100' ; 4
	retlw		b'11001100' ; 4
	retlw		b'11001100' ; 4
	retlw		b'11011010' ; 5
	retlw		b'11011010' ; 5
	retlw		b'11011010' ; 5
	retlw		b'11011010' ; 5
	retlw		b'11011010' ; 5
	retlw		b'11111010' ; 6
	retlw		b'11111010' ; 6
	retlw		b'11111010' ; 6
	retlw		b'11111010' ; 6
	retlw		b'11111010' ; 6
	retlw		b'00001110' ; 7
	retlw		b'00001110' ; 7
	retlw		b'00001110' ; 7
	retlw		b'00001110' ; 7
	retlw		b'00001110' ; 7
	retlw		b'11111110' ; 8
	retlw		b'11111110' ; 8
	retlw		b'11111110' ; 8
	retlw		b'11111110' ; 8
	retlw		b'11111110' ; 8
	retlw		b'11001110' ; 9
	retlw		b'11001110' ; 9
	retlw		b'11001110' ; 9
	retlw		b'11001110' ; 9
	retlw		b'11001110' ; 9
	retlw		b'01111110' ; 0		5
	retlw		b'01111110' ; 0
	retlw		b'01111110' ; 0
	retlw		b'01111110' ; 0*****
	retlw		b'01111110' ; 0
	retlw		b'01111110' ; 0

	return

LeftDigitLookUpTable				; BCD conversion table
	retlw		b'01111111' ; 0		0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'01111111' ; 0
	retlw		b'00001101' ; 1		1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'00001101' ; 1
	retlw		b'10110111' ; 2		2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10110111' ; 2
	retlw		b'10011111' ; 3		3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'10011111' ; 3
	retlw		b'11001101' ; 4		4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11001101' ; 4
	retlw		b'11011011' ; 5		5
	retlw		b'11011011' ; 5
	retlw		b'11011011' ; 5
	retlw		b'11011011' ; 5*****
	retlw		b'11011011' ; 5
	retlw		b'11011011' ; 5


end


